/* Verilog model created from schematic top_module.sch -- Nov 21, 2012 15:31 */

module top_module( ADC_ampl, ADC_clk, ADC_data_ready, control_bit_sampling_or_no_data,
                   control_bit_state_0, control_bit_state_1, data_bus_to_MCU,
                   data_clk, external_clck, reset );
 input [11:0] ADC_ampl;
output ADC_clk;
 input ADC_data_ready;
output control_bit_sampling_or_no_data;
 input control_bit_state_0;
 input control_bit_state_1;
output [7:0] data_bus_to_MCU;
 input data_clk;
 input external_clck;
 input reset;
  wire [31:0] sample_counter_to_FIFO;

  wire [7:0] sample_ADC_FIFO;

  wire [7:0] sample_counter_FIFO;

  wire [31:0] c;

  wire [15:0] sample_ADC_to_FIFO;

wire logic_low;

wire FIFO_empty_buffered;

wire FIFO_full_buffered;

wire clk_inv;

wire FIFO_R_clk_buffered;

wire logic_high;

wire reset_req;

wire start_sampling_ORed;

wire FIFO_full;

wire FIFO_empty;

wire currently_sampling;

wire no_more_data_to_transfer;

wire FIFO_W_clk;

wire sample_counter_FIFO_RdEn;

wire sample_ADC_FIFO_RdEn;

wire FIFO_R_clk;

wire N_6;

wire N_7;

wire N_8;

wire N_9;

wire N_10;

wire N_11;

wire reset_counter;

wire clk;




INV I26 ( .A(clk), .Z(clk_inv) );
FD1P3IX I25 ( .CD(reset), .CK(clk_inv), .D(FIFO_R_clk), .Q(FIFO_R_clk_buffered),
           .SP(logic_high) );
FD1P3IX I27 ( .CD(reset), .CK(clk_inv), .D(FIFO_empty), .Q(FIFO_empty_buffered),
           .SP(logic_high) );
FD1P3IX I28 ( .CD(reset), .CK(clk_inv), .D(FIFO_full), .Q(FIFO_full_buffered),
           .SP(logic_high) );
PLL_27_200 I18 ( .CLK(external_clck), .CLKOP(clk), .RESET(reset) );
AND2 I14 ( .A(control_bit_state_0), .B(control_bit_state_1), .Z(reset_req) );
OR2 I15 ( .A(control_bit_state_0), .B(control_bit_state_1),
       .Z(start_sampling_ORed) );
OR2 I13 ( .A(currently_sampling), .B(no_more_data_to_transfer),
       .Z(control_bit_sampling_or_no_data) );
VLO I11 ( .Z(logic_low) );
VLO I21 ( .Z(sample_ADC_to_FIFO[12]) );
VLO I22 ( .Z(sample_ADC_to_FIFO[13]) );
VLO I23 ( .Z(sample_ADC_to_FIFO[14]) );
VLO I24 ( .Z(sample_ADC_to_FIFO[15]) );
VHI I12 ( .Z(logic_high) );
data_deliverer I8 ( .clk(clk), .currently_sampling(currently_sampling),
                 .data_bus_to_MCU(data_bus_to_MCU[7:0]),
                 .data_clk(data_clk), .FIFO_empty(FIFO_empty_buffered),
                 .FIFO_R_clk(FIFO_R_clk),
                 .no_more_data_to_transfer(no_more_data_to_transfer),
                 .reset(reset), .sample_ADC_FIFO(sample_ADC_FIFO[7:0]),
                 .sample_ADC_FIFO_RdEn(sample_ADC_FIFO_RdEn),
                 .sample_counter_FIFO(sample_counter_FIFO[7:0]),
                 .sample_counter_FIFO_RdEn(sample_counter_FIFO_RdEn) );
sample_data_points I9 ( .ADC_ampl(ADC_ampl[11:0]),
                     .ADC_data_ready(ADC_data_ready), .clk(clk),
                     .counter(c[31:0]),
                     .currently_sampling(currently_sampling),
                     .FIFO_full(FIFO_full_buffered),
                     .FIFO_W_clk(FIFO_W_clk),
                     .no_more_data_to_transfer(no_more_data_to_transfer),
                     .reset(reset),
                     .sample_ADC_to_FIFO(sample_ADC_to_FIFO[11:0]),
                     .sample_counter_to_FIFO(sample_counter_to_FIFO[31:0]),
                     .start_sampling_ORed(start_sampling_ORed) );
FIFO_counter I19 ( .AlmostEmpty(N_11), .AlmostFull(N_10),
                .Data(sample_counter_to_FIFO[31:0]), .Empty(FIFO_empty),
                .Full(FIFO_full), .Q(sample_counter_FIFO[7:0]),
                .RdClock(FIFO_R_clk_buffered),
                .RdEn(sample_counter_FIFO_RdEn), .Reset(reset),
                .RPReset(reset), .WrClock(FIFO_W_clk), .WrEn(logic_high) );
MUX21 I6 ( .D0(c[5]), .D1(c[0]), .SD(currently_sampling), .Z(ADC_clk) );
counter I10 ( .clk(clk), .counter(c[31:0]), .reset(reset_counter) );
counter_resetter I2 ( .ADC_ampl(ADC_ampl[11:0]), .clk(clk), .reset(reset),
                   .reset_counter(reset_counter), .reset_req(reset_req) );
FIFO_ampl I20 ( .AlmostEmpty(N_8), .AlmostFull(N_9),
             .Data(sample_ADC_to_FIFO[15:0]), .Empty(N_6), .Full(N_7),
             .Q(sample_ADC_FIFO[7:0]), .RdClock(FIFO_R_clk_buffered),
             .RdEn(sample_ADC_FIFO_RdEn), .Reset(reset), .RPReset(reset),
             .WrClock(FIFO_W_clk), .WrEn(logic_high) );

endmodule // top_module
